1. Field of the Invention
The present invention relates to a semiconductor device (e.g., a memory device) including fuses used, variously, for redundant circuitry or programming. For example, fuses are formed in a decoder of a static random-access memory (SRAM).
2. Description of the Related Art
A fuse of the semiconductor device is blown, as needed and using an electric current pulse or laser, for replacing a defective circuit with a redundant circuit or for programming (writing) information in a memory cell. A partial structure of the semiconductor device including a fuse has been designed to prevent an electrical short-circuit between a semiconductor substrate and a circuit including the fuse from occurring and to prevent moisture from entering into an interior of the device from the atmosphere.
Two conventional semiconductor devices with a fuse are now explained with reference to FIGS. 1A, 1B, 2A and 2B, respectively.
As shown in FIGS. 1A and lB, a portion of a first conventional semiconductor device including a fuse comprises a semiconductor substrate 1 consisting of a p-type silicon base substrate 2 and an n-type epitaxial silicon layer 3 formed thereon. In the epitaxial layer 3 a p-type isolation region 4 of a rectangular ring configuration (FIG. 1A) is formed to extend in the base substrate 2, so that a portion 3A of the epitaxial layer, below a narrow blowable portion 5A of a fuse 5, is isolated from the base substrate 2 and the other portion i.e., the portion exterior of the isolation region 4) of the epitaxial layer 3. On the substrate 1 (i.e., on the epitaxial layer 3), a field oxide layer 6 of SiO.sub.2 is formed. The fuse 5 of polycrystalline silicon, aluminum or other metal is formed on the field oxide layer 6 and has the narrow portion 5A (FIG. 1A) to be blown. An insulating layer 7 of, e.g., PSG (phosphosilicate glass) is formed over the fuse 5 and the field oxide layer 6 for isolating lower interconnections (conductive lines) including the fuse from upper interconnections. Furthermore, a passivation layer 8 of, e.g., PSG is formed on the insulating layer 7, and a nitride layer 9 of, e.g., Si.sub.3 N.sub.4 is formed on the passivation layer 8. Since the passivation PSG layer 8 is hygroscopicity (i.e., has low moisture-resistance), the nitride layer 9 having a high moisture-resistance prevents moisture from penetrating into the semiconductor device. The layers 9 and 8 are selectively etched to form an opening 10 above the narrow portion 5A.
As the occasion demands, the narrow portion 5A of the fuse 5 is irradiated with a laser beam through the opening 10, or a pulse current is fed through the fuse 5, so as to blow the fuse 5 by breaking the narrow portion 5A. The opening 10 facilitates the breaking of the narrow portion, and the insulating layer 7 prevents the broken portion from splashing (i.e., being disposed).
When fusing, the broken portion of the fuse 5 may cause damage (cracks) to the field oxide layer 6, which may to extend into the epitaxial layer 3, producing a short circuit between the fuse 5 and the epitaxial layer 3 and thereby causing trouble. The isolation region 4 is formed to prevent the short from causing trouble.
As shown in FIGS. 2A and 2B, a portion of a second conventional semiconductor device including a fuse comprises a semiconductor substrate 11 and a field oxide layer 16 of SiO.sub.2 formed on the substrate. The substrate 11 may consist of a silicon base substrate and an epitaxial layer (layer shown) formed thereon. A fuse 15 with a narrow blowable portion 15A is made of polycrystalline silicon, aluminum or other metal and is formed on the field oxide layer 16. An insulating layer of, e.g., PSG is formed over the fuse 15 and the field oxide layer 16 for isolating lower interconnections (conductive lines) including the fuse from upper interconnections. The insulating layer 17 is selectively etched to form a groove 17, surrounding the narrow portion 15A, except for two displaced, or separated, portions or gaps therein corresponding to the fuse 15. A metal guard ring 21 of, e.g., aluminum is formed to overfill the groove and come into contact with the field oxide layer 16. The guard ring 21 is separated into two portions each having a light channel shape (i.e., a cross-sectional shape of a light weight metal channel), as shown in FIG. 2A.
As mentioned above, in the first conventional device, a passivation layer 18 of, e.g., PSG is formed over the metal guard ring 21 and the insulating layer 17, and a nitride layer 19 of , e.g., Si.sub.3 N.sub.4 is formed on the passivation layer 18. The layers 19 and 18 are selectively etched to form an opening 20 above the narrow portion 15A. The fuse 15 is blown by breaking the narrow portion 15A with a laser beam or a pulse current. Of course, some of a number of the fuses are selectively blown in accordance with demands, while the majority of the fuses are not blown.
Since portions of the insulating 17 and the passivation layer 18 are exposed in the opening 20, moisture penetrates into the inside of the device through the layers 17 and 18. To prevent the moisture penetration, the metal guard ring 21 is formed so as to vertically extend through the insulating layer 17 and thereby to separate the portion of the layer 17 adjacent to and surrounding the narrow portion 15A from the rest thereof.
However, in the first conventional semiconductor device (FIGS. 1A and 1B), the moisture penetrates into the inside of the device, through the insulating layer 7 and the interface between the layers 7 and 8 from the exposed portion of the layer 7 within the opening 10. The moisture which penetrates to the inside deteriorates aluminum interconnections (lines) and active elements (e.g., transistors) of the device. Furthermore, when the cracks of the insulating layer 6 and the passivation layer 7 are caused by blowing the fuse 5, moisture may penetrate through the respective interfaces between the layers 6 and 7 and between the epitaxial layer 3 and the layer 6 from the cracks. In the second conventional semiconductor device (FIGS. 2A and 2B), when blowing the fuse 15, cracks in the layers 16 and 17 may also occur and cause trouble, such as a short circuit or moisture penetration.
The nitride layer 9 (or 19) of the first (or second) semiconductor device is formed to protect the passivation PSG layer 8 (or 18) except for the opening 10 (or 20), with the result that a side of the layer 8 (or 18) and a portion of the layer 7 (or 17) are exposed in the opening. Therefore, the nitride layer does not sufficiently contribute to improving the moisture-resistance of the semiconductor device.